The Chair +QCHIP at the University of Granada is launching a first series of free, in-person microcredentials as part of its microcredentials program in “Innovative Microelectronic Circuit Design.” Tailored for graduates in engineering and architecture, these specialized courses support Spain’s strategic growth in the semiconductor sector. Each microcredential combines advanced theoretical content with hands-on experience in the University’s state-of-the-art Clean Room facilities. Taught in English by leading experts, this initial group of microcredentials will run through September 2025—with more diverse offerings to follow in the coming months.
Below are the details of the upcoming microcredentials:
Semiconductor Physics and Optoelectronics Devices
– Dates: May 26 – July 18, 2025
– Enrollment: May 06 – May 22, 2025
– Credits: 5 ECTS
– Hours: 125
– Location: CITIC-UGR
– Schedule: Mon–Fri, 9h–13h & 16h–19h
– Link: Semiconductor Physics and Optoelectronics Devices
Nanoelectronics Technologies: CMOS and New Materials
– Dates: June 9 – September 5, 2025
– Enrollment: May 7 – June 2, 2025
– Credits: 5 ECTS
– Hours: 125
– Location: CITIC-UGR
– Schedule: Mon–Fri, 9h–13h & 16h–19h
– Link: Nanoelectronics Technologies
Structural and Electrical Characterization of Devices
– Dates: June 30 – September 19, 2025
– Enrollment: May 12 – June 22, 2025
– Credits: 5 ECTS
– Hours: 125
– Location: CITIC-UGR
– Schedule: Mon–Fri, 9h–13h & 16h–19h
– Link: Structural and Electrical Characterization
Integrated Circuit Design with Open-Source Tools
– Dates: July 14 – September 30, 2025
– Enrollment: May 14 – July 6, 2025
– Credits: 5 ECTS
– Hours: 125
– Location: CITIC-UGR
– Schedule: Mon–Fri, 9h–13h & 16h–19h
– Link: Integrated Circuit Design
Innovation on Nanoelectronics
– Dates: July 28 – October 10, 2025
– Enrollment: May 20 – July 20, 2025
– Credits: 3 ECTS
– Hours: 75
– Location: CITIC-UGR
– Schedule: Mon–Fri, 9h–13h & 16h–19h
– Link: Innovation on Nanoelectronics
Integrated Circuit Test Tools
– Dates: September 8 – October 31, 2025
– Enrollment: May 20 – August 31, 2025
– Credits: 5 ECTS
– Hours: 125
– Location: CITIC-UGR
– Schedule: Mon–Fri, 9h–13h & 16h–19h
– Link: Integrated Circuit Test Tools
Actuación TSI-069100-2023-0003 cofinanciada por la Unión Europea. +QCHIP: Transformando la industria de semiconductores a través de la integración monolítica de circuitos CMOS y tecnologías innovadoras. Proyecto financiado por la Secretaría de Estado de Telecomunicaciones e Infraestructuras Digitales, Ministerio para la Transformación Digital y de la Función Pública. Convocatoria 2023 para la creación de cátedras universidad-empresa (Cátedras Chip). Financiado por la Unión Europea-NextGenerationEU